TY - CHAP A1 - Wenzl, Matthias A1 - Fibich, Christian A1 - Rössler, Peter A1 - Taucher, Herbert A1 - Matschnig, Martin T1 - Logic Synthesis of Assertions for Saftey-critical Applications T2 - Proceedings of the 2015 International Conference on Industrial Technology (ICIT), March 17-19, 2015 KW - Safety Y1 - ER - TY - GEN A1 - Wenzl, Matthias A1 - Fibich, Christian A1 - Rössler, Peter A1 - Taucher, Herbert A1 - Matschnig, Martin T1 - Logic Synthesis of Assertions for Saftey-critical Applications KW - Safety Y1 - ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - HLShield: A Reliability Enhancement Framework for High-Level Synthesis T2 - 12th IEEE International Symposium on Industrial Embedded Systems (SIES 2017) KW - Embedded Systems Y1 - 2018 ER - TY - CHAP A1 - Fibich, Christian A1 - Rössler, Peter A1 - Tauner, Stefan A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - A FPGA-based Demonstrator for Safety-Critical Applications T2 - IEEE Austria Austrochip 2017, Oct. 12, 2017, Linz KW - Embedded Systems KW - FPGA Y1 - 2019 ER - TY - CHAP A1 - Fibich, Christian A1 - Wenzl, Matthias A1 - Rössler, Peter T1 - On Automated Generation of Checker Units from Hardware Assertion Languages T2 - Proceedings of the Microelectronic Systems Symposium 2014 (MESS'14), May 8-9, Vienna, 2014 KW - Embedded Systems Y1 - 2019 ER - TY - GEN A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu KW - FPGA KW - HLS KW - High-Level Synthesis Y1 - ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin T1 - Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures T2 - Proceedings of the 2020 15th Conference on Computer Science and Information Systems (FedCSIS), 6-9 September 2020, Sofia, Bulgaria KW - Embedded Systems KW - Basic Linear Algebra Subprograms KW - Benchmarks KW - ARM KW - RISC-V Y1 - SP - 663 EP - 672 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs T2 - Proceedings of the 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-5 February 2021, Grenoble, France KW - FPGA KW - Fault Injection KW - Device Variations Y1 - SP - 1600 EP - 1605 ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Krapfenbauer, Markus A1 - Linauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications T2 - 8th Mediterranean Conference on Embedded Computing (MECO), co-sponsored by IEEE, June 10-14, 2019, Budva, Montenegro KW - Embedded Systems KW - Basic Linear Algebra Subprograms KW - BLAS KW - Benchmark Y1 - 2019 ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu T2 - IEEE 13th International Symposium on Industrial Embedded Systems (SIES), Graz, 2018 KW - FPGA KW - HLS KW - High-Level Synthesis Y1 - 2018 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Reliability-Enhanced High-Level Synthesis using Memory Profiling and Fault Injection T2 - 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), Vancouver, BC, Canada, 2019 KW - Circuit faults KW - Reliability engineering KW - Field programmable gate arrays KW - Fault tolerance KW - Fault tolerant systems Y1 - 2019 SP - 1363 EP - 1370 ER - TY - JOUR A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - FIJI – Fault InJection Instrumenter JF - EURASIP Journal on Embedded Systems KW - Fault injection KW - FPGA KW - Safety-critical system KW - Verification KW - Electronic design automation Y1 - 2019 VL - 2019 IS - Februar 2019 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Vulnerability Analysis of Storage Elements in HLS-Generated Designs using High-Level Profiling T2 - Proceedings of the 2nd International Conference on System Reliability and Safety (ICSRS2017), 20-22 December 2017, Milan, Italy KW - High-Level Synthesis KW - Functional Safety KW - FPGA Y1 - 2017 SP - 190 EP - 194 ER - TY - JOUR A1 - Fibich, Christian A1 - Rössler, Peter A1 - Tauner, Stefan A1 - Taucher, Herbert A1 - Matschnig, Martin T1 - A Netlist-level Fault-injection Tool for FPGAs JF - e & i Elektrotechnik und Informationstechnik: Volume 132, Issue 6 (2015) KW - FPGA KW - Embedded Systems KW - Electronic Engineering KW - Information Technology Y1 - 2019 IS - e & i Elektrotechnik und Informationstechnik: Volume 132, Issue 6 (2015) ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Characterization of Interconnect Fault Effects in SRAM-based FPGAs T2 - Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023), 3-5 May 2023, Tallinn, Estonia KW - Soft Errors KW - FPGA KW - Interconnect Fault Y1 - U6 - http://dx.doi.org/https://doi.org/10.1109/DDECS57882.2023.10139343 SP - 65 EP - 68 ER - TY - JOUR A1 - Fibich, Christian A1 - Schmitt, Patrick A1 - Höller, Roland A1 - Rössler, Peter T1 - Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation JF - International Journal of Reconfigurable Computing KW - Ethernet KW - FPGA KW - Design Reuse KW - IP Core KW - Open Source Y1 - U6 - http://dx.doi.org/https://doi.org/10.1155/2023/9222318 VL - 2023 SP - Article ID 9222318 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Bitstream-Level Interconnect Fault Characterization for SRAM-based FPGAs T2 - Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE 2023), pp. 1-2, 16-18 April 2023, Antwerp, Belgium KW - FPGA KW - Fault Injection KW - Interconnect Fault Y1 - U6 - http://dx.doi.org/10.23919/DATE56975.2023.10136911 ER -