TY - JOUR A1 - Rössler, Peter A1 - Höller, Roland T1 - Programmable Logic Devices – Key Components for Today's and Tomorrow's Electronic-Based Systems JF - e&i (Elektrotechnik und Informationstechnik), Volume 137, Issue 1, 2020 KW - Programmable Logic Devices KW - Field-Programmable Gate Arrays KW - PLD KW - FPGA Y1 - 2020 VL - Vol. 137, 2020 IS - Issue 1, 2020 ER - TY - CHAP A1 - Rössler, Peter A1 - Höller, Roland A1 - Reisner, Christopher A1 - Schrön, Felix A1 - Ewers, Ekaterina T1 - A Model Railway based Demonstrator for Saftey-Critical Systems T2 - 12th European Workshop on Microelectronics Education, Sept. 24-26, 2018, Braunschweig, Germany KW - Functional Safety KW - FPGA KW - PSoC KW - Distributed System KW - Education Y1 - 2019 ER - TY - CHAP A1 - Rössler, Peter A1 - Höller, Roland T1 - Innovative Plattformen für Elektronische Systeme (INES) T2 - Proceedings of the FFH (Forschungsforum der Östereichischen Fachhochschulen), April 24-25, 2019, Wiener Neustadt, Austria KW - FPGA KW - Field-Programmable Gate Array KW - PLD KW - Programmable Logic Device KW - Electronic Based Systems Y1 - 2019 ER - TY - CHAP A1 - Billmann, Maurice A1 - Werner, Stefan A1 - Höller, Roland A1 - Praus, Friedrich A1 - Puhm, Andreas A1 - Kerö, Nikolaus T1 - Open-Source Crypto IP Cores for FPGAs - Overview and Evaluation T2 - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria KW - open-source cryptography IP cores KW - FPGA KW - advanced encryption standard KW - secure hash algorithm KW - physically unclonable function Y1 - 2020 ER - TY - JOUR A1 - Fibich, Christian A1 - Schmitt, Patrick A1 - Höller, Roland A1 - Rössler, Peter T1 - Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation JF - International Journal of Reconfigurable Computing KW - Ethernet KW - FPGA KW - Design Reuse KW - IP Core KW - Open Source Y1 - U6 - http://dx.doi.org/https://doi.org/10.1155/2023/9222318 VL - 2023 SP - Article ID 9222318 ER -