TY  - CHAP
A1  - Billmann, Maurice
A1  - Werner, Stefan
A1  - Höller, Roland
A1  - Praus, Friedrich
A1  - Puhm, Andreas
A1  - Kerö, Nikolaus
T1  - Open-Source Crypto IP Cores for FPGAs - Overview and Evaluation
T2  - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria
KW  - open-source cryptography IP cores
KW  - FPGA
KW  - advanced encryption standard
KW  - secure hash algorithm
KW  - physically unclonable function
Y1  - 2020
ER  - 
TY  - CHAP
A1  - Muhr, H.
A1  - Höller, Roland
T1  - Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression
T2  - Proceedings of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), July 17-20, Samos, Greece
KW  - Simulation
KW  - Clock Suppression
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Guenes, Serkan
A1  - Stipek, Philipp
A1  - Höller, Roland
T1  - Hardware Implementation of a Transform Coding Stage for a Video Decoder
T2  - Proceedings of Austrochip 2006, 11 October, Vienna, Austria
KW  - Video Decoder
KW  - Hardware
Y1  - 2019
SP  - 209
EP  - 216
ER  - 
TY  - JOUR
A1  - Fibich, Christian
A1  - Schmitt, Patrick
A1  - Höller, Roland
A1  - Rössler, Peter
T1  - Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
JF  - International Journal of Reconfigurable Computing
KW  - Ethernet
KW  - FPGA
KW  - Design Reuse
KW  - IP Core
KW  - Open Source
Y1  - 
U6  - http://dx.doi.org/https://doi.org/10.1155/2023/9222318
VL  - 2023
SP  - Article ID 9222318
ER  -