TY  - GEN
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Horauer, Martin
A1  - Obermaisser, Roman
T1  - Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs
T2  - Proceedings of the 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-5 February 2021, Grenoble, France
KW  - FPGA
KW  - Fault Injection
KW  - Device Variations
Y1  - 
SP  - 1600
EP  - 1605
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
T2  - IEEE 13th International Symposium on Industrial Embedded Systems (SIES), Graz, 2018
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 2018
ER  - 
TY  - JOUR
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - FIJI – Fault InJection Instrumenter
JF  - EURASIP Journal on Embedded Systems
KW  - Fault injection
KW  - FPGA
KW  - Safety-critical system
KW  - Verification
KW  - Electronic design automation
Y1  - 2019
VL  - 2019
IS  - Februar 2019
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Horauer, Martin
A1  - Obermaisser, Roman
T1  - Vulnerability Analysis of Storage Elements in HLS-Generated Designs using High-Level Profiling
T2  - Proceedings of the 2nd International Conference on System Reliability and Safety (ICSRS2017), 20-22 December 2017, Milan, Italy
KW  - High-Level Synthesis
KW  - Functional Safety
KW  - FPGA
Y1  - 2017
SP  - 190
EP  - 194
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Horauer, Martin
A1  - Obermaisser, Roman
T1  - Characterization of Interconnect Fault Effects in SRAM-based FPGAs
T2  - Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023), 3-5 May 2023, Tallinn, Estonia
KW  - Soft Errors
KW  - FPGA
KW  - Interconnect Fault
Y1  - 
U6  - http://dx.doi.org/https://doi.org/10.1109/DDECS57882.2023.10139343
SP  - 65
EP  - 68
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Horauer, Martin
A1  - Obermaisser, Roman
T1  - Bitstream-Level Interconnect Fault Characterization for SRAM-based FPGAs
T2  - Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE 2023), pp. 1-2, 16-18 April 2023, Antwerp, Belgium
KW  - FPGA
KW  - Fault Injection
KW  - Interconnect Fault
Y1  - 
U6  - http://dx.doi.org/10.23919/DATE56975.2023.10136911
ER  -