TY  - CHAP
A1  - Baumgartner, Daniel
A1  - Rössler, Peter
A1  - Kubinger, Wilfried
T1  - Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms
T2  - IEEE Conference on Computer Vision and Pattern Recognition (CVPR '07), p. 1-8, 23rd June 2007, Minneapolis, Minnesota, USA
KW  - Embedded Systems
KW  - FPGA
Y1  - 2019
SN  - 1-4244-1180-7
SP  - 1
EP  - 8
ER  - 
TY  - CHAP
A1  - Baumgartner, Daniel
A1  - Kubinger, Wilfried
A1  - Rössler, Peter
T1  - Optimization and Benchmark of Vision Algorithms on a DSP
T2  - Proceedings of the 18th International DAAAM Symposium on Intelligent Manufacturing & Automation, October 24-27 2007, Zadar, Croatia
KW  - Embedded Systems
KW  - Algorithm
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Veigl, Christoph
A1  - Kutschera, Christof
A1  - Rössler, Peter
T1  - Ausgelagerte Uhrensynchronisation für verteilte eingebettete Systeme
T2  - 3. Forschungsforum der österreichischen Fachhochschulen (FFH2009), Villach, Austria, April 15-16 2009
KW  - Embedded Systems
KW  - Synchronization
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Eckel, C.
A1  - Bodenstorfer, E.
A1  - Nachtnebel, H.
A1  - Rössler, Peter
A1  - Fürtler, J.
A1  - Mayer, K.
T1  - Hochgeschwindigkeitskamera mit intelligenter Datenvorverarbeitung
T2  - Proceedings of Austrochip 2006, 11 October, Vienna, Austria
KW  - Camera
KW  - Data Processing
Y1  - 2019
SP  - 103
EP  - 108
ER  - 
TY  - CHAP
A1  - Jakisch, Philipp
A1  - Krammer, Christopher
A1  - Krätz, Thomas
A1  - Stukelj, Gasper
A1  - Werdenits, Lukas
A1  - Höller, Roland
A1  - Rössler, Peter
T1  - Field Programmable Analog Circuits and Arrays – An Overview
T2  - Proceedings of the IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, Dec. 9-10, 2021
KW  - Field Programmable Analog Arrays
KW  - FPAA
KW  - Mixed-Signal I/O Circuits
Y1  - 
ER  - 
TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
A1  - Reisner, Christopher
A1  - Maischberger, Oliver
T1  - Survey and Comparison of Digital Logic Simulators
T2  - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria
KW  - Digital Logic Simulation
KW  - Verification
KW  - Electronic Design Automation
KW  - VLSI Design
KW  - Survey
Y1  - 2020
ER  - 
TY  - CHAP
A1  - Höller, Roland
A1  - Haselberger, Dominic
A1  - Ballek, Dominik
A1  - Rössler, Peter
T1  - Open-Source RISC-V Processor IP Cores for FPGAs – Overview and Evaluation
T2  - 8th Mediterranean Conference on Embedded Computing (MECO), co-sponsored by IEEE, June 10-14, 2019, Budva, Montenegro
KW  - Field-Programmable Gate Array
KW  - PSoC
KW  - CPU Core
KW  - Open-Source
KW  - RISC-V
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
A1  - Reisner, Christopher
A1  - Schrön, Felix
A1  - Ewers, Ekaterina
T1  - A Model Railway based Demonstrator for Saftey-Critical Systems
T2  - 12th European Workshop on Microelectronics Education, Sept. 24-26, 2018, Braunschweig, Germany
KW  - Functional Safety
KW  - FPGA
KW  - PSoC
KW  - Distributed System
KW  - Education
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Wenzl, Matthias
A1  - Rössler, Peter
A1  - Puhm, Andreas
T1  - Checking Application-level Properties Using Assertion Synthesis
T2  - Proceedings of the ASME/IEEE International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, August 18-21, 2019, Anaheim, CA, USA
KW  - Assertion-based Verification
KW  - PSL
KW  - Assertion Synthesis
KW  - Fault Detection
KW  - FPGA
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
T1  - Innovative Plattformen für Elektronische Systeme (INES)
T2  - Proceedings of the FFH (Forschungsforum der Östereichischen Fachhochschulen), April 24-25, 2019, Wiener Neustadt, Austria
KW  - FPGA
KW  - Field-Programmable Gate Array
KW  - PLD
KW  - Programmable Logic Device
KW  - Electronic Based Systems
Y1  - 2019
ER  -