TY  - CHAP
A1  - Baumgartner, Daniel
A1  - Rössler, Peter
A1  - Kubinger, Wilfried
T1  - Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms
T2  - IEEE Conference on Computer Vision and Pattern Recognition (CVPR '07), p. 1-8, 23rd June 2007, Minneapolis, Minnesota, USA
KW  - Embedded Systems
KW  - FPGA
Y1  - 2019
SN  - 1-4244-1180-7
SP  - 1
EP  - 8
ER  - 
TY  - JOUR
A1  - Rössler, Peter
A1  - Höller, Roland
T1  - Programmable Logic Devices – Key Components for Today's and Tomorrow's Electronic-Based Systems
JF  - e&i (Elektrotechnik und Informationstechnik), Volume 137, Issue 1, 2020
KW  - Programmable Logic Devices
KW  - Field-Programmable Gate Arrays
KW  - PLD
KW  - FPGA
Y1  - 2020
VL  - Vol. 137, 2020
IS  - Issue 1, 2020
ER  - 
TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
A1  - Reisner, Christopher
A1  - Schrön, Felix
A1  - Ewers, Ekaterina
T1  - A Model Railway based Demonstrator for Saftey-Critical Systems
T2  - 12th European Workshop on Microelectronics Education, Sept. 24-26, 2018, Braunschweig, Germany
KW  - Functional Safety
KW  - FPGA
KW  - PSoC
KW  - Distributed System
KW  - Education
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Wenzl, Matthias
A1  - Rössler, Peter
A1  - Puhm, Andreas
T1  - Checking Application-level Properties Using Assertion Synthesis
T2  - Proceedings of the ASME/IEEE International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, August 18-21, 2019, Anaheim, CA, USA
KW  - Assertion-based Verification
KW  - PSL
KW  - Assertion Synthesis
KW  - Fault Detection
KW  - FPGA
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
T1  - Innovative Plattformen für Elektronische Systeme (INES)
T2  - Proceedings of the FFH (Forschungsforum der Östereichischen Fachhochschulen), April 24-25, 2019, Wiener Neustadt, Austria
KW  - FPGA
KW  - Field-Programmable Gate Array
KW  - PLD
KW  - Programmable Logic Device
KW  - Electronic Based Systems
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Fürtler, J.
A1  - Brodersen, J.
A1  - Rössler, Peter et al.
T1  - Architecture for Hardware-driven Image Inspection based on FPGAs
T2  - Proceedings of the SPIE Electronic Imaging 2006 Conference, Volume 6063, 15-19 January, San Jose, USA
KW  - Hardware Architecture
KW  - Image Inspection
KW  - FPGA
Y1  - 2019
SP  - 105
EP  - 113
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Rössler, Peter
A1  - Tauner, Stefan
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - A FPGA-based Demonstrator for Safety-Critical Applications
T2  - IEEE Austria Austrochip 2017, Oct. 12, 2017, Linz
KW  - Embedded Systems
KW  - FPGA
Y1  - 2019
ER  - 
TY  - GEN
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
T2  - IEEE 13th International Symposium on Industrial Embedded Systems (SIES), Graz, 2018
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 2018
ER  - 
TY  - JOUR
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - FIJI – Fault InJection Instrumenter
JF  - EURASIP Journal on Embedded Systems
KW  - Fault injection
KW  - FPGA
KW  - Safety-critical system
KW  - Verification
KW  - Electronic design automation
Y1  - 2019
VL  - 2019
IS  - Februar 2019
ER  - 
TY  - JOUR
A1  - Fibich, Christian
A1  - Rössler, Peter
A1  - Tauner, Stefan
A1  - Taucher, Herbert
A1  - Matschnig, Martin
T1  - A Netlist-level Fault-injection Tool for FPGAs
JF  - e & i Elektrotechnik und Informationstechnik: Volume 132, Issue 6 (2015)
KW  - FPGA
KW  - Embedded Systems
KW  - Electronic Engineering
KW  - Information Technology
Y1  - 2019
IS  - e & i Elektrotechnik und Informationstechnik: Volume 132, Issue 6 (2015)
ER  - 
TY  - JOUR
A1  - Fibich, Christian
A1  - Schmitt, Patrick
A1  - Höller, Roland
A1  - Rössler, Peter
T1  - Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
JF  - International Journal of Reconfigurable Computing
KW  - Ethernet
KW  - FPGA
KW  - Design Reuse
KW  - IP Core
KW  - Open Source
Y1  - 
U6  - http://dx.doi.org/https://doi.org/10.1155/2023/9222318
VL  - 2023
SP  - Article ID 9222318
ER  -