TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
A1  - Reisner, Christopher
A1  - Maischberger, Oliver
T1  - Survey and Comparison of Digital Logic Simulators
T2  - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria
KW  - Digital Logic Simulation
KW  - Verification
KW  - Electronic Design Automation
KW  - VLSI Design
KW  - Survey
Y1  - 2020
ER  -