TY  - CHAP
A1  - Fürtler, J.
A1  - Brodersen, J.
A1  - Rössler, Peter et al.
T1  - Architecture for Hardware-driven Image Inspection based on FPGAs
T2  - Proceedings of the SPIE Electronic Imaging 2006 Conference, Volume 6063, 15-19 January, San Jose, USA
KW  - Hardware Architecture
KW  - Image Inspection
KW  - FPGA
Y1  - 2019
SP  - 105
EP  - 113
ER  - 
TY  - JOUR
A1  - Fürtler, Johannes
A1  - Rössler, Peter
T1  - Design Considerations for Scalable High Performance Vision Systems Embedded in Industrial Print Inspection Machines
JF  - EURASIP International Journal on Embedded Systems, Special Issue on "Embedded Vision Systems"
KW  - Embedded Systems
KW  - Industrial Print
Y1  - 2019
VL  - Volume 2007
IS  - Article ID 71794
ER  - 
TY  - CHAP
A1  - Wenzl, Matthias
A1  - Fibich, Christian
A1  - Rössler, Peter
A1  - Taucher, Herbert
A1  - Matschnig, Martin
T1  - Logic Synthesis of Assertions for Saftey-critical Applications
T2  - Proceedings of the 2015 International Conference on Industrial Technology (ICIT), March 17-19, 2015
KW  - Safety
Y1  - 
ER  - 
TY  - GEN
A1  - Wenzl, Matthias
A1  - Fibich, Christian
A1  - Rössler, Peter
A1  - Taucher, Herbert
A1  - Matschnig, Martin
T1  - Logic Synthesis of Assertions for Saftey-critical Applications
KW  - Safety
Y1  - 
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Rössler, Peter
A1  - Tauner, Stefan
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - A FPGA-based Demonstrator for Safety-Critical Applications
T2  - IEEE Austria Austrochip 2017, Oct. 12, 2017, Linz
KW  - Embedded Systems
KW  - FPGA
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Wenzl, Matthias
A1  - Rössler, Peter
T1  - On Automated Generation of Checker Units from Hardware Assertion Languages
T2  - Proceedings of the Microelectronic Systems Symposium 2014 (MESS'14), May 8-9, Vienna, 2014
KW  - Embedded Systems
Y1  - 2019
ER  - 
TY  - GEN
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
T1  - Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures
T2  - Proceedings of the 2020 15th Conference on Computer Science and Information Systems (FedCSIS), 6-9 September 2020, Sofia, Bulgaria
KW  - Embedded Systems
KW  - Basic Linear Algebra Subprograms
KW  - Benchmarks
KW  - ARM
KW  - RISC-V
Y1  - 
SP  - 663
EP  - 672
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Krapfenbauer, Markus
A1  - Linauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications
T2  - 8th Mediterranean Conference on Embedded Computing (MECO), co-sponsored by IEEE, June 10-14, 2019, Budva, Montenegro
KW  - Embedded Systems
KW  - Basic Linear Algebra Subprograms
KW  - BLAS
KW  - Benchmark
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Tauner, Stefan
A1  - Rössler, Peter
A1  - Horauer, Martin
A1  - Matschnig, Martin
A1  - Taucher, Herbert
T1  - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
T2  - IEEE 13th International Symposium on Industrial Embedded Systems (SIES), Graz, 2018
KW  - FPGA
KW  - HLS
KW  - High-Level Synthesis
Y1  - 2018
ER  -