TY  - CHAP
A1  - Muhr, H.
A1  - Höller, Roland
T1  - Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression
T2  - Proceedings of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), July 17-20, Samos, Greece
KW  - Simulation
KW  - Clock Suppression
Y1  - 2019
ER  -