TY  - CHAP
A1  - Rössler, Peter
A1  - Höller, Roland
A1  - Reisner, Christopher
A1  - Schrön, Felix
A1  - Ewers, Ekaterina
T1  - A Model Railway based Demonstrator for Saftey-Critical Systems
T2  - 12th European Workshop on Microelectronics Education, Sept. 24-26, 2018, Braunschweig, Germany
KW  - Functional Safety
KW  - FPGA
KW  - PSoC
KW  - Distributed System
KW  - Education
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Fibich, Christian
A1  - Horauer, Martin
A1  - Obermaisser, Roman
T1  - Vulnerability Analysis of Storage Elements in HLS-Generated Designs using High-Level Profiling
T2  - Proceedings of the 2nd International Conference on System Reliability and Safety (ICSRS2017), 20-22 December 2017, Milan, Italy
KW  - High-Level Synthesis
KW  - Functional Safety
KW  - FPGA
Y1  - 2017
SP  - 190
EP  - 194
ER  -