TY  - CHAP
A1  - Eckel, C.
A1  - Bodenstorfer, E.
A1  - Nachtnebel, H.
A1  - Rössler, Peter
A1  - Fürtler, J.
A1  - Mayer, K.
T1  - Hochgeschwindigkeitskamera mit intelligenter Datenvorverarbeitung
T2  - Proceedings of Austrochip 2006, 11 October, Vienna, Austria
KW  - Camera
KW  - Data Processing
Y1  - 2019
SP  - 103
EP  - 108
ER  - 
TY  - CHAP
A1  - Fürtler, J.
A1  - Brodersen, J.
A1  - Rössler, Peter et al.
T1  - Architecture for Hardware-driven Image Inspection based on FPGAs
T2  - Proceedings of the SPIE Electronic Imaging 2006 Conference, Volume 6063, 15-19 January, San Jose, USA
KW  - Hardware Architecture
KW  - Image Inspection
KW  - FPGA
Y1  - 2019
SP  - 105
EP  - 113
ER  - 
TY  - CHAP
A1  - Muhr, Hannes
A1  - Höller, Roland
A1  - Horauer, Martin
T1  - A Heterogenous Hardware-Software Co-Simulation Environment Using User Mode Linux and Clock Suppression
T2  - Proceedings of the 2nd IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA 2006), August 13-16, Beijing, China
KW  - Hardware
KW  - Linux
KW  - Clock Suppression
KW  - Simulation
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Armengaud, Eric
A1  - Steininger, Andreas
A1  - Horauer, Martin
T1  - Automatic Parameter Identification in FlexRay based Automotive Communication Networks
T2  - Proceedings of the 11th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2006), September, Prague, Czech Republic
KW  - Automotive
KW  - Communication Network
Y1  - 2019
SP  - 897
EP  - 904
ER  - 
TY  - CHAP
A1  - Armengaud, Eric
A1  - Steininger, Andreas
A1  - Horauer, Martin
T1  - An Efficient Test and Diganosis Environment for Communication Controllers
T2  - Proceedings of Austrochip 2006, 11 October, Vienna, Austria
KW  - Testing
KW  - Communication Controller
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Schreiner, Dietmar
A1  - Göschka, Karl
T1  - Model Level Validation of Component Based Software for Distributed Embedded Systems
T2  - Proceedings of the 20th European Conference on Object-Oriented Programming (ECCOP 2006), July 3-7, Nantes, France
KW  - Embedded Systems
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Muhr, H.
A1  - Höller, Roland
T1  - Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression
T2  - Proceedings of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), July 17-20, Samos, Greece
KW  - Simulation
KW  - Clock Suppression
Y1  - 2019
ER  - 
TY  - CHAP
A1  - Guenes, Serkan
A1  - Stipek, Philipp
A1  - Höller, Roland
T1  - Hardware Implementation of a Transform Coding Stage for a Video Decoder
T2  - Proceedings of Austrochip 2006, 11 October, Vienna, Austria
KW  - Video Decoder
KW  - Hardware
Y1  - 2019
SP  - 209
EP  - 216
ER  -