TY - CHAP A1 - Jakisch, Philipp A1 - Krammer, Christopher A1 - Krätz, Thomas A1 - Stukelj, Gasper A1 - Werdenits, Lukas A1 - Höller, Roland A1 - Rössler, Peter T1 - Field Programmable Analog Circuits and Arrays – An Overview T2 - Proceedings of the IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, Dec. 9-10, 2021 KW - Field Programmable Analog Arrays KW - FPAA KW - Mixed-Signal I/O Circuits Y1 - ER - TY - CHAP A1 - Rössler, Peter A1 - Höller, Roland A1 - Reisner, Christopher A1 - Maischberger, Oliver T1 - Survey and Comparison of Digital Logic Simulators T2 - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria KW - Digital Logic Simulation KW - Verification KW - Electronic Design Automation KW - VLSI Design KW - Survey Y1 - 2020 ER - TY - JOUR A1 - Rössler, Peter A1 - Höller, Roland T1 - Programmable Logic Devices – Key Components for Today's and Tomorrow's Electronic-Based Systems JF - e&i (Elektrotechnik und Informationstechnik), Volume 137, Issue 1, 2020 KW - Programmable Logic Devices KW - Field-Programmable Gate Arrays KW - PLD KW - FPGA Y1 - 2020 VL - Vol. 137, 2020 IS - Issue 1, 2020 ER - TY - CHAP A1 - Höller, Roland A1 - Haselberger, Dominic A1 - Ballek, Dominik A1 - Rössler, Peter T1 - Open-Source RISC-V Processor IP Cores for FPGAs – Overview and Evaluation T2 - 8th Mediterranean Conference on Embedded Computing (MECO), co-sponsored by IEEE, June 10-14, 2019, Budva, Montenegro KW - Field-Programmable Gate Array KW - PSoC KW - CPU Core KW - Open-Source KW - RISC-V Y1 - 2019 ER - TY - CHAP A1 - Rössler, Peter A1 - Höller, Roland A1 - Reisner, Christopher A1 - Schrön, Felix A1 - Ewers, Ekaterina T1 - A Model Railway based Demonstrator for Saftey-Critical Systems T2 - 12th European Workshop on Microelectronics Education, Sept. 24-26, 2018, Braunschweig, Germany KW - Functional Safety KW - FPGA KW - PSoC KW - Distributed System KW - Education Y1 - 2019 ER - TY - CHAP A1 - Wenzl, Matthias A1 - Rössler, Peter A1 - Puhm, Andreas T1 - Checking Application-level Properties Using Assertion Synthesis T2 - Proceedings of the ASME/IEEE International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, August 18-21, 2019, Anaheim, CA, USA KW - Assertion-based Verification KW - PSL KW - Assertion Synthesis KW - Fault Detection KW - FPGA Y1 - 2019 ER - TY - CHAP A1 - Rössler, Peter A1 - Höller, Roland T1 - Innovative Plattformen für Elektronische Systeme (INES) T2 - Proceedings of the FFH (Forschungsforum der Östereichischen Fachhochschulen), April 24-25, 2019, Wiener Neustadt, Austria KW - FPGA KW - Field-Programmable Gate Array KW - PLD KW - Programmable Logic Device KW - Electronic Based Systems Y1 - 2019 ER - TY - CHAP A1 - Kramer, Michael A1 - Gerstmayer, Florian A1 - Hausladen, Jürgen T1 - Evaluation of Libraries and Typical Embedded Systems for ECDSA Signature Verification for Car2X Communication T2 - 2018 IEEE 23rd International Conference on Emerging Technologies and Factory Automation (ETFA), Turin, Italy, 2018 KW - Digital Signature KW - Cryptography KW - Security KW - Verification KW - Car2X communication Y1 - 2018 SP - 1123 EP - 1126 ER - TY - CHAP A1 - Billmann, Maurice A1 - Werner, Stefan A1 - Höller, Roland A1 - Praus, Friedrich A1 - Puhm, Andreas A1 - Kerö, Nikolaus T1 - Open-Source Crypto IP Cores for FPGAs - Overview and Evaluation T2 - Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria KW - open-source cryptography IP cores KW - FPGA KW - advanced encryption standard KW - secure hash algorithm KW - physically unclonable function Y1 - 2020 ER - TY - JOUR A1 - Kerö, Nikolaus A1 - Puhm, Andreas A1 - Kernen, Thomas A1 - Mroczkowski, Anton T1 - Performance and Reliability Aspects of Clock Synchronization Techniques for Industrial Automation JF - Proceedings of the IEEE KW - Precision Time Protocol KW - PTP KW - IEEE 1588 KW - Reliable KW - Clock Synchronization Y1 - 2019 VL - Vol. 107 IS - No. 6 SP - 1011 EP - 1026 ER - TY - GEN A1 - Kramer, Michael A1 - Gerstmayer, Florian A1 - Hausladen, Jürgen T1 - Evaluation of Libraries and Typical Embedded Systems for ECDSA Signature Verification for Car2X Communication KW - Digital Signature KW - Cryptography KW - Security KW - Verification KW - Car2X communication Y1 - ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin T1 - Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures T2 - Proceedings of the 2020 15th Conference on Computer Science and Information Systems (FedCSIS), 6-9 September 2020, Sofia, Bulgaria KW - Embedded Systems KW - Basic Linear Algebra Subprograms KW - Benchmarks KW - ARM KW - RISC-V Y1 - SP - 663 EP - 672 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs T2 - Proceedings of the 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-5 February 2021, Grenoble, France KW - FPGA KW - Fault Injection KW - Device Variations Y1 - SP - 1600 EP - 1605 ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Krapfenbauer, Markus A1 - Linauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications T2 - 8th Mediterranean Conference on Embedded Computing (MECO), co-sponsored by IEEE, June 10-14, 2019, Budva, Montenegro KW - Embedded Systems KW - Basic Linear Algebra Subprograms KW - BLAS KW - Benchmark Y1 - 2019 ER - TY - CHAP A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu T2 - IEEE 13th International Symposium on Industrial Embedded Systems (SIES), Graz, 2018 KW - FPGA KW - HLS KW - High-Level Synthesis Y1 - 2018 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Reliability-Enhanced High-Level Synthesis using Memory Profiling and Fault Injection T2 - 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), Vancouver, BC, Canada, 2019 KW - Circuit faults KW - Reliability engineering KW - Field programmable gate arrays KW - Fault tolerance KW - Fault tolerant systems Y1 - 2019 SP - 1363 EP - 1370 ER - TY - JOUR A1 - Fibich, Christian A1 - Tauner, Stefan A1 - Rössler, Peter A1 - Horauer, Martin A1 - Matschnig, Martin A1 - Taucher, Herbert T1 - FIJI – Fault InJection Instrumenter JF - EURASIP Journal on Embedded Systems KW - Fault injection KW - FPGA KW - Safety-critical system KW - Verification KW - Electronic design automation Y1 - 2019 VL - 2019 IS - Februar 2019 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Vulnerability Analysis of Storage Elements in HLS-Generated Designs using High-Level Profiling T2 - Proceedings of the 2nd International Conference on System Reliability and Safety (ICSRS2017), 20-22 December 2017, Milan, Italy KW - High-Level Synthesis KW - Functional Safety KW - FPGA Y1 - 2017 SP - 190 EP - 194 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Characterization of Interconnect Fault Effects in SRAM-based FPGAs T2 - Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023), 3-5 May 2023, Tallinn, Estonia KW - Soft Errors KW - FPGA KW - Interconnect Fault Y1 - U6 - http://dx.doi.org/https://doi.org/10.1109/DDECS57882.2023.10139343 SP - 65 EP - 68 ER - TY - JOUR A1 - Fibich, Christian A1 - Schmitt, Patrick A1 - Höller, Roland A1 - Rössler, Peter T1 - Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation JF - International Journal of Reconfigurable Computing KW - Ethernet KW - FPGA KW - Design Reuse KW - IP Core KW - Open Source Y1 - U6 - http://dx.doi.org/https://doi.org/10.1155/2023/9222318 VL - 2023 SP - Article ID 9222318 ER - TY - CHAP A1 - Fibich, Christian A1 - Horauer, Martin A1 - Obermaisser, Roman T1 - Bitstream-Level Interconnect Fault Characterization for SRAM-based FPGAs T2 - Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE 2023), pp. 1-2, 16-18 April 2023, Antwerp, Belgium KW - FPGA KW - Fault Injection KW - Interconnect Fault Y1 - U6 - http://dx.doi.org/10.23919/DATE56975.2023.10136911 ER -