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Survey and Comparison of Digital Logic Simulators

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Metadaten
Author:Peter Rössler, Roland Höller, Christopher Reisner, Oliver Maischberger
Parent Title (English):Proceedings of 27th Austrochip Conference on Microelectronics, Oct. 24, 2019, Vienna, Austria
Document Type:Conference Proceeding
Language:English
Completed Date:2019/09/24
Date of first Publication:2020/11/03
Responsibility for metadata:Fachhochschule Technikum Wien
Release Date:2020/11/03
GND Keyword:Digital Logic Simulation; Electronic Design Automation; Survey; VLSI Design; Verification
Pagenumber:5
Publish on Website:1
Open Access:0
Reviewed:1
Invited:0
Keynote:0
Department:Department Electronic Engineering
Dewey Decimal Classification:6 Technik, Medizin, angewandte Wissenschaften / 62 Ingenieurwissenschaften
Research Focus:Embedded Systems & Cyber-Physical Systems
Projects:CDG
Studienjahr:2019/2020