Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression
| Author: | H. Muhr, Roland Höller |
|---|---|
| Parent Title (English): | Proceedings of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), July 17-20, Samos, Greece |
| Document Type: | Conference Proceeding |
| Language: | English |
| Completed Date: | 2006/07/17 |
| Date of first Publication: | 2019/01/31 |
| Responsibility for metadata: | Fachhochschule Technikum Wien |
| Release Date: | 2019/01/31 |
| GND Keyword: | Clock Suppression; Simulation |
| Publish on Website: | 1 |
| Open Access: | 0 |
| Reviewed: | 0 |
| Invited: | 0 |
| Keynote: | 0 |
| Department: | Department Electronic Engineering |
| Research Focus: | Embedded Systems & Cyber-Physical Systems |
| Studienjahr: | 2005/2006 |
| Projects: | Import |
