Checking Application-level Properties Using Assertion Synthesis
| Author: | Matthias Wenzl, Peter Rössler, Andreas Puhm |
|---|---|
| Parent Title (English): | Proceedings of the ASME/IEEE International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, August 18-21, 2019, Anaheim, CA, USA |
| Document Type: | Conference Proceeding |
| Language: | English |
| Completed Date: | 2019/08/18 |
| Date of first Publication: | 2019/10/30 |
| Responsibility for metadata: | Fachhochschule Technikum Wien |
| Release Date: | 2019/10/30 |
| GND Keyword: | Assertion Synthesis; Assertion-based Verification; FPGA; Fault Detection; PSL |
| Pagenumber: | 9 |
| Publish on Website: | 1 |
| Open Access: | 0 |
| Reviewed: | 1 |
| Invited: | 0 |
| Keynote: | 0 |
| Department: | Department Electronic Engineering |
| Dewey Decimal Classification: | 6 Technik, Medizin, angewandte Wissenschaften / 62 Ingenieurwissenschaften |
| Research Focus: | Embedded Systems & Cyber-Physical Systems |
| Projects: | CDG |
| Studienjahr: | 2018/2019 |
